Field
The present disclosure generally relates to methods and apparatus for controlling photoresist line width roughness and, more specifically, to methods and apparatus for controlling photoresist line width roughness with enhanced electron spin control in semiconductor processing technologies.
Description
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g. to sub-micron dimensions), more elements are required to be put in a given area of a semiconductor integrated circuit. Accordingly, lithography process has become more and more challenging to transfer even smaller features onto a substrate precisely and accurately without damage. In order to transfer precise and accurate features onto a substrate, a desired high resolution lithography process requires having a suitable light source that may provide a radiation at a desired wavelength range for exposure. Furthermore, the lithography process requires transferring features onto a photoresist layer with minimum photoresist line width roughness (LWR). After all, a defect-free photomask is required to transfer desired features onto the photoresist layer. Recently, an extreme ultraviolet (EUV) radiation source has been utilized to provide short exposure wavelengths so as to provide a further reduced minimum printable size on a substrate. However, at such small dimensions, the roughness of the edges of a photoresist layer has become harder and harder to control.
FIG. 1 depicts an exemplary top isometric sectional view of a substrate 100 having a patterned photoresist layer 104 disposed on a target material 102 to be etched. Openings 106 are defined between the patterned photoresist layer 104 readily to expose the underlying target material 102 for etching to transfer features onto the target material 102. However, inaccurate control or low resolution of the lithography exposure process may cause in poor critical dimension control in the photoresist layer 104, thereby resulting in unacceptable line width roughness (LWR) 108. Large line width roughness (LWR) 108 of the photoresist layer 104 may result in inaccurate feature transfer to the target material 102, thus, eventually leading to device failure and yield loss.
Therefore, there is a need for a method and an apparatus to control and minimize line width roughness (LWR) so as to obtain a patterned photoresist layer with desired critical dimensions.